1. Field of the Invention
The present disclosure relates to the field of fabrication of microstructures, and, more particularly, to a method for defining microstructure features on the basis of nano imprint techniques.
2. Description of the Related Art
Fabrication of microstructures, such as integrated circuits, requires tiny regions of precisely controlled size to be formed in a material layer of an appropriate substrate, such as a silicon substrate. These tiny regions of precisely controlled size are generated by patterning the material layer, for instance, by performing photolithography and etch processes. For this purpose, in conventional semiconductor techniques, a mask layer is formed over the material layer under consideration to first define these tiny regions in the mask layer. Generally, a mask layer may consist of or is formed by means of a layer of photoresist that is patterned by a lithographic process, such as a photolithography process. During a typical photolithography process, the resist may be spin-coated onto the wafer surface and is then selectively exposed to ultraviolet radiation. After developing the photoresist, depending on the type of resist, positive resist or negative resist, the exposed portions or the non-exposed portions are removed to form the required pattern in the layer of photoresist. Since the dimensions of the patterns in sophisticated integrated circuits are steadily decreasing, the equipment used for patterning device features have to meet very stringent requirements with regard to resolution and overlay accuracy of the involved fabrication processes. In this respect, resolution is considered as a measure specifying the consistent ability to print minimum size images under conditions of predefined manufacturing variations. One important factor in improving the resolution is represented by the photolithography process, in which patterns contained in a photo mask or reticle are optically transferred to the substrate via an optical imaging system. Therefore, great efforts are made to steadily improve optical properties of the lithographic system, such as numerical aperture, depth of focus and wavelength of the light source used.
The quality of the lithographic imagery is extremely important in creating very small feature sizes. Of at least comparable importance, however, is the accuracy with which an image can be positioned on the surface of the substrate. Many types of microstructures, such as integrated circuits, are fabricated by sequentially patterning material layers, wherein features on successive material layers bear a well-defined spatial relationship to one another. Each pattern formed in a subsequent material layer has to be aligned to a corresponding pattern formed in the previously patterned material layer within specified registration tolerances. These registration tolerances are caused by, for example, a variation of a photoresist image on the substrate due to non-uniformities in such parameters as resist thickness, baking temperature, exposure and development. Furthermore, non-uniformities of the etching processes can also lead to variations of the etched features. In addition, there exists an uncertainty in overlaying the image of the pattern for the current material layer to the etched pattern of the previously formed material layer while photolithographically transferring the image onto the substrate. Several factors contribute to the ability of the imagery system to perfectly overlay two layers, such as imperfections within a set of masks, temperature differences at the different times of exposure and a limited registration capability of the alignment tool. As a result, the dominant criteria, determining the minimum feature size that may finally be obtained, are the resolution for creating features in individual substrate layers and the total overlay error to which the above explained factors, in particular the lithographic process, contribute.
The continuous scaling of microstructures requires a corresponding adaptation of photolithography systems with respect to exposure wavelength, beam optics, alignment means and the like in order to provide the required resolution, which, however, places a high burden on the tool manufacturers in view of development efforts, while the manufacturers of microstructures are confronted with increasing tool investments and significant cost of ownership. Hence, new techniques have been proposed for defining microstructure features in respective material layers, while avoiding or reducing some of the problems associated with conventional photolithography techniques. One promising approach is the nano imprint technique, which is a method for mechanically transferring a pattern defined in a mold or die into an appropriate mask layer, which may then be used for patterning the material layer under consideration. For example, during the manufacturing of metallization layers of sophisticated semiconductor devices, requiring metal structures with reduced feature sizes, low parasitic capacitance and high resistance against electromigration, usually the so-called inlaid or damascene technique is used. In this technology for forming wiring layers that provide the complex circuit layout of integrated circuits, an appropriate dielectric material is patterned to receive trenches and vias, which are subsequently filled with a highly conductive material, such as copper, copper alloys, silver or any other suitable metal. Hence, the vias, providing the electrical connection between metal regions of different stacked metallization layers, have to be precisely aligned with respect to the metal regions, such as metal lines, wherein the lateral dimensions of the metal lines and vias, at least in lower-lying metallization layers, are comparable to the minimum critical dimensions, thereby requiring highly sophisticated lithography techniques. In addition, the surface topography in higher device layers may have to be thoroughly controlled for optical patterning techniques, which may require highly sophisticated planarization techniques due to the usage of low-k dielectric materials, which may have a reduced mechanical stability compared to “conventional” dielectric materials, such as silicon dioxide, silicon nitride and the like. Thus, by avoiding an optical patterning regime, respective trenches or vias may be formed on the basis of nano imprint techniques, wherein a resist material or any other mask material is contacted by a corresponding die having a relief that includes respective lines and spaces for forming trenches, when trenches for metal lines are to be formed. In a next process step, the mask layer may be used to transfer the pattern from the mask layer into the material layer, such as the dielectric material of the metallization layer.
Although many problems associated with photolithography may be avoided by using the nano imprint technique, the trenches defined by the imprint process have to be precisely aligned to previously formed vias, thereby also imposing very stringent constraints on the imprint process technique. In other situations, the nano imprint technique suffers from reduced flexibility with respect to the shaping of openings when directly formed in an interlayer dielectric material, since then the adjustment of exposure and/or etch parameters for obtaining, for instance, a tapered shape, as is used as an efficient control regime in conventional photolithography techniques, may no longer be available.
The present disclosure is directed to various methods that may solve, or at least reduce, some or all of the aforementioned problems.